The present invention relates to integrated circuits, and more particularly, to clock generator circuits that generate clock signals with selected frequency characteristics.
In a modern electronic system, there are always numerous integrated circuits that operate in a synchronous manner. In these kinds of electronic systems, the generation of periodic clock signals for clocking the operation of different circuit functions with a basic system clock (or a synchronization pulse) is an essential task that must be carefully performed.
FIG. 1 shows a clock generator circuit of the related art. The clock generator circuit 100 shown in this figure includes a multiplexer 120, an accumulator 125, and a toggle circuit 140. The accumulator 125 is made up of a register 130, which is a first delay flip-flop (DFF) in this example, and an adder 150. The toggle circuit 140 is a second DFF in this example. There are N reference clock signals being fed into the multiplexer 120. Each of the reference clock signals has the same period TREF but a different phase, wherein the phase difference between any two adjacent reference clock signals is a constant value which is TREF/N in this example. In other words, phase difference among the plurality of reference clock signals is the times of the constant value.
The multiplexer 120 selects a reference clock signal from the plurality of reference clock signals to generate a first clock signal C1 according to a selection code SC received from the first DFF 130. The accumulator 125 generates the selection code SC by accumulating a fixed frequency code FC. More specifically, the adder 150 adds the fixed frequency code FC with the selection code SC fed back by the first DFF 130 to generate a preliminary selection code PSC, and the preliminary selection code PSC is used by the first DFF 130 to generate the selection code SC. The first DFF 130 operates in accordance with the first clock signal C1, hence each time a rising edge occurs in the first clock signal C1 (which is provided by one of the reference clock signals fed into the multiplexer 120), a newly generated selection code SC will be used to switch the multiplexer 120 and be fed back to the adder 150. The second DFF 140 is clocked by the first clock signal C1, and an input of the second DFF 140 receives an output clock signal COUT generated by an inverted output of the second DFF 140. Each time a rising edge occurs in the first clock signal C1 (which is provided by one of the reference clock signals fed into the multiplexer 120), the state of the output clock signal COUT will be inverted once.
The fixed frequency code FC is for controlling the clock generator circuit 100, indicating the number of adjacent phase(s) of the reference clock signals fed into the multiplexer 120 are going to be elapsed between two rising edges of the first clock signal C1. As for the output clock signal COUT, the fixed frequency code FC indicates the number of adjacent phase(s) of the reference clock signals fed into the multiplexer 120 are going to be elapsed between each pair of adjacent rising edge and falling edge of the output clock signal COUT. Hence the frequency of the output clock signal COUT is digitally controlled by the frequency code FC. Assuming that each of the N reference clock signals fed into the multiplexer 120 have a same frequency fREF and the frequency code FC is set as 1, the output clock signal COUT will have a frequency equal to (N/2)×fREF. By setting the frequency code FC as 2, the output clock signal COUT will have a frequency equal to (N/4)×fREF. Additionally, by setting the frequency code FC as n (where 1≦n≦N), the output clock signal COUT will have a frequency equal to (N/2n)×fREF. In the clock generator circuit 100 of the related art, the number of possible frequencies that the output clock signal COUT could have is quite limited and is determined by the number N of the reference clock signals. It is therefore desired to provide a new clock generator circuit that can generate an output clock signal with a larger selection of possible frequencies.